1. Field of the Invention
The present invention relates to an IC tester. In particular, the present invention is directed to a tester which is suited for quick generation of a long LSI test pattern.
2. Description of the Related Art
An LSI tester consists of (1) a pattern generator which generates input patterns to be given to an input pin of an LSI under test and expected patterns for comparison with the value of the output pin, (2) a timing generator which generates the timing to give the input patterns mentioned above and the timing for comparison with the expected patterns mentioned above, (3) a wave formatter which formats a digital wave used for the test using the patterns and timing generated from the generators mentioned above, and (4) a comparator which compares the output patterns of the LSI under test and the expected patterns.
The pattern generator stores the input patterns and expected patterns in the memory beforehand, and reads and generates the patterns when the test is to be executed. The tester is equipped with an address controller which controls reading of the memory for repetitive generation of the same pattern or for generation of a pattern jump. The memory stores the patterns as well as address control instructions to generate complicated patterns.
There is an increasing demand for increased speed of such an LSI tester as mentioned above, especially a pattern generator due to high speed operation of semiconductors. Japanese Patent Laid-Open 1982-111471, "Test Pattern Generator" is associated with this demand.
In this generator, the test patterns and the address control instructions are stored in independent memories, and the patterns are read in more than one cycle during execution of one address control instruction. The memory storing the address control instructions and the address controller (program counter) are provided with a 1/N divided clock. Access to the memory storing the patterns is made by the address generated by the address controller and an address, to the lower part of which the output of the base N counter is set. During execution of one address control instruction, the base N counter generates the lower part from 0 to N-1 of an address to read the patterns. By doing this, patterns can be generated at a speed N times of the operation speed of the address controller.
The conventional method mentioned above has a disadvantage in that the number of patterns to be read by one address control instruction is fixed to 1:N and pattern read cannot be optionally controlled or pattern read is restricted considerably, causing a limit to speedup of pattern read.